In recent years, high quality and high speed are demanded of a DVD-ROM, which has become widespread as a digital memory, to increase the reliability of data read from a DVD disk. With the demand, a signal processor for correcting errors in the disk is required to have rapid processing means, and it is aimed at realization of high-speed data processing.
A conventional CD-ROM signal processor performs error correction by a predetermined number of times. Further, the CD-ROM signal processor writes inputted data in a buffer memory and, simultaneously, detects errors in the data by using CRC (Cyclic Redundancy Check). Based on the result of CRC, when the data is decided as “error-free data”, the signal processor reduces the predetermined number of error corrections.
In the case of DVD-ROM data, however, since inputted data is not previously subjected to error correction in contrast to the CD-ROM data, the error rate is higher in the DVD-ROM data than in the CD-ROM data. Therefore, when the DVD-ROM data is subjected to CRC, the result of CRC is, in most cases, that there are errors in the DVD-ROM data.
FIG. 6 is a block diagram illustrating the structure of a conventional DVD-ROM signal processor.
In FIG. 6, a DVD-ROM signal processor 65 receives DVD-ROM digital signal data (hereinafter referred to as “data”) which is read by an optical pickup 61, and outputs the data after error correction to a host computer 63. The DVD-ROM signal processor 65 is under control of a control microcomputer 62, and is connected with a buffer memory 64 which stores data.
To be specific, the DVD-ROM signal processor 65 is provided with an FMT block 651 for capturing the DVD-ROM data outputted from the optical pickup 61, and storing it in the buffer memory 64; an error correction block 652 for correcting errors in the data stored in the buffer memory 64; a descrambling block 653 for descrambling the scrambled data; an error detection block 654 for detecting errors in the data after error correction, which data is stored in the buffer memory 64; a host interface block 655 for transmitting error-free data to the host computer, based on the result of the error detection by the error detection block 654; and a memory interface block 656 for controlling the processing between the DVD-ROM signal processor 65 and the buffer memory 64.
The operation of the conventional DVD-ROM signal processor so constructed will be described with reference to FIGS. 4 and 6.
FIG. 4 is a diagram illustrating the data format constituting one ECC block.
As shown in FIG. 4, the logical format of the DVD-ROM data outputted from the optical pickup 61 is constituted with 182×208 bytes as one ECC (Error Correcting Code) block.
First of all, the data read by the optical pickup 61 forms one component unit with 182 bytes as a C1 code word. The C1 code word is composed of 172 bytes of user data and 10 bytes of C1 parity. One ECC block is composed of plural C1 code words and plural C2 code words, each C2 code word comprising 208 bytes obtained by collecting one byte from each Cl code word. Each C2 code word is composed of 192 bytes of user data and 16 bytes of C2 parity. The DVD-ROM data has been scrambled in advance.
In FIG. 6, the FMT block 651 converts the DVD-ROM serial data outputted from the optical pickup 61 into parallel data (serial to parallel conversion), subjects the converted data to demodulation and sync detection, and writes the parallel data in the buffer memory 64 through the memory interface block 656.
The error correction block 652 reads the DVD-ROM data written in the buffer memory 64, through the memory interface block 656, performs syndrome calculation on the C1 code words and the C2 code words shown in FIG. 4, and calculates the error position and the error pattern by using the result of the syndrome calculation. Based on the result of the syndrome calculation, the error correction block 652 terminates the error correction when the data has no error. However, when the data has some error, the error correction block 652 reads the error data stored in the buffer memory 64, through the memory interface block 656, performs error correction on the error data, and writes the corrected data over the address of the error data stored in the buffer memory 64, through the memory interface block 656.
The descrambling block 653 reads the DVD-ROM data which has been subjected to error correction and is stored in the buffer memory 64, through the memory interface block 656, descrambles the data according to a predetermined method, and writes the data in the buffer memory 64 through the memory interface block 656.
The error detection block 654 reads the DVD-ROM data which has been descrambled and is stored in the buffer memory 64, through the memory interface block 656, and detects errors in the read data by performing a predetermined calculation.
The host interface block 655 transmits, to the host computer 63, the DVD-ROM data which has been decided as “error-free data” in both of the error correction block 652 and the error detection block 654.
Each of the above-mentioned blocks is constructed so as to operate at a predetermined timing according to an instruction from the control microcomputer 62.
In the conventional DVD-ROM signal processor, however, when the DVD-ROM data is subjected to error correction, the following operations are performed on the buffer memory 64: writing of data from the FMT block 651, reading and writing of data from the error correction block 652, reading and writing of data from the descrambling block 653, reading of data from the error detection block 654, and reading of data from the host interface block 655. That is, since reading and writing of data are performed frequently through the buffer memory 64, the memory band width is pressed and, therefore, the signal processor cannot perform high-speed access and higher-speed data processing.
The present invention is made to solve the above-described problem, and it is an object of the present invention to provide a signal processor which can reduce the number of memory accesses by reducing the number of error corrections, thereby realizing higher-speed data processing.